Variable Delay Timing Analysis of Logic Circuits

We propose a new simulation algorithm for combinational circuits which accurately models delay variations in the gates. The algorithm can also be used for the timing veriication of asynchronous circuits, eg hazard detection, race/oscillation of sequential circuits, etc. The basic idea is to assign a time variable to each signal transition (edge). The gate delays translate to algebraic relations between the variables. As the arrival order of the edges to a gate can be uncertain, so the simulation result of the gate can diverge. Branching signal paths are introduced to deal with this problem. However the simulation process later often does not depend on earlier branching. The algorithm takes advantage of such cases. We believe that this leads to considerable eeciency improvements. educational or research purposes on condition that (1) this copyright notice is included, (2) proper attribution to the author or authors is made and (3) no commercial gain is involved.